User Programmable 48 Channel TTL I/O IP Module- DATA PATTERNS

Product ID	DP-IP-5433
Product Name	User Programmable 48 Channel TTL I/O IP Module
Product Description	DP-IP-5433 is a user programmable 48 channel TTL I/O module. This module provides an user programmable FPGA on an Industry Pack (IP) module.The FPGA can control up to 48 TTL signals. The 48 channels are divided into six groups of eight channels each. Each group can be configured as input or output independently.User application programs are downloaded through the IP bus directly into the FPGA. A pre-programmed internal CPLD facilitates initialization by acting as the bus controller during power-up while the program is downloading. After downloading the program, the FPGA takes control of the IP bus and disables the CPLD. IP modules are suitable for use in any hardware platforms such as cPCI, VME, VXI and PCI through carrier. Flexibility in front or rear I/O routing is provided by the availability of carrier modules.
Key Features	Altera EP1K100 FPGA. 48 TTL I/O lines in 6 groups of 8 channels. FPGA programmable via the IP bus. FPGA controlled local static RAM (64K x 16). Programmable PLL-based clock synthesizer (1MHz - 100MHz). Example FPGA design code provided as VHDL. 8MHz IP bus interface. Digital I/O control register. Hardware support for DMA and memory space. Windows 2000 drivers provided. RT Linux drivers provided.
Datasheet